A typical circuit of one phase of a three-level single-phase inverter or multi-phase inverter has the configuration shown in FIG. 11 of the present application. The inverter here means a circuit for converting a DC power into an AC power but also obviously converts an AC power into a DC power.
In FIG. 11, reference numeral 1 represents a DC power source, the voltage of which is divided by capacitors 2, 3 to form three potentials, P, M and N. Reference numerals 4 to 7 each represent a semiconductor switching element capable of intermittently controlling a forward current and constantly allowing passage of a reverse current. The semiconductor switching elements are each shown with a MOSFET (metal-oxide-semiconductor field-effect transistor) and a diode connected antiparallel thereto. The semiconductor switching elements 6 and 7 are connected in series in the directions opposite to each other and configured into a so-called bidirectional switch that is capable of intermittently controlling both forward and reverse currents. The semiconductor switching elements 4 and 5 are connected in series and configured into a vertical arm 11 corresponding to one phase. As opposed to the vertical arm 11, the bidirectional switch configured by connected the semiconductor switching elements 6 and 7 in series is called “intermediate arm 12.”
In FIG. 11, the potential of an AC output terminal U is equivalent to the potential of a high-potential terminal P of the DC power source 1 when the semiconductor switching element 4 of the vertical arm 11 is on, and becomes equivalent to the potential of a lower-potential terminal N of the DC power source 1 when the semiconductor switching element 5 is on. When the semiconductor switching element 6 or 7 of the intermediate arm is on, the potential of the AC output terminal U becomes equivalent to the potential of an intermediate point M between the two capacitors 2 and 3, i.e., the intermediate potential of the DC power source 1.
In other words, the circuit shown in FIG. 11 forms a three-level inverter capable of selecting three voltage levels for the potential of the AC output terminal U in accordance with the ON state of each semiconductor switching element.
In such a three-level inverter circuit that generates outputs in three levels, a withstand voltage of each of the semiconductor switching elements 6 and 7 forming the intermediate arm 12 only needs to be half of that of each of the semiconductor elements 4 and 5 forming the vertical arm 11. In addition, depending on the operation conditions (power factor and modulation factor), conduction loss and switching loss that occur in each of the semiconductor switching elements forming the vertical arm and the intermediate arm vary. For this reason, the specifications of the semiconductor switching elements of the vertical arm and the intermediate arm that are suitable for the withstand voltages, switching characteristics and the like vary depending on the operational condition of a device to which this circuit is applied.
Furthermore, in a circuit that uses semiconductor switching elements, typically a surge voltage occurs due to the current changing rate (di/dt) obtained at the time of a switching operation and a parasitic inductance on the circuit. The surge voltage is a cause of overvoltage of a semiconductor switching element, which is often problematic. Since this problem similarly occurs in the three-level inverter circuit described above, parasitic inductances of DC circulating current paths need to be minimized.
In response to this need, PTL 1 discloses a technique for reducing wiring inductances by forming three connection conductors, i.e., a connection conductor connected to a high-potential point P, a connection conductor connected to an intermediate-potential point M, and a connection conductor connected to a low-potential point N, into flat conductors and arranging these flat conductors adjacent to each other with insulators therebetween, to form a laminated structure.
FIGS. 12(a) and 12(b) show the wiring structure described in PTL 1. FIGS. 12(a) and 12(b) show the wiring structure of a three-phase three-level inverter, wherein references Cd1 to Cd4 represent DC capacitors, reference numerals 18, 19 and 20 represent phase modules in which the semiconductor switching elements shown in FIG. 11 are stored, reference numeral 29 represents a flat P-potential connection conductor bar, reference numeral 30 represents a flat M-potential connection conductor bar, and reference numeral 31 represents a flat N-potential connection conductor bar. The DC capacitors Cd1 to Cd4 are disposed in a Y-direction shown in the diagram, which is the horizontal direction of the phase modules 18, 19 and 20. The flat connection conductor bars 29, 30 and 31 are configured into a connection conductor bar having a laminated structure, by stacking them with insulation sheets 32 and 33 therebetween. As is generally known, a connection conductor bar having a laminated structure can reduce parasitic inductances of the conductor parts by means of offsetting of the magnetic fluxes of the currents reciprocating in the conductors.